Open Positions

 

 

Director of Hardware Engineering (Sunnyvale, CA)

• Work with marketing & applications to generate product specifications

• Generate suitable architectures to support target solution

• Oversee development activities of hardware team members and provide mentoring when necessary
  Ensure programs are meeting quality and schedule commitments

• Identify risk factor early in the process and prioritize their resolution

• Support clean production ramp

• Ensure quality documentation and review process are occurring with team

• 15+ years of HW design exp – 5+ years in a leading role is a plus

• Must have experience and/or be very familiar with product design flow stages from concept to production 

• Solid experience in board level design including analog, low noise, control loops, sensors, EMI, etc.

• Experience with power mgmt. and digital domains

• Solid understanding of the engineering process, including error budgeting, hardware and software topics, ability to diagnose and debug systems issues

• Exp. with electrical and safety certification process and working with ISO approved process flows

• Strong team building/leading and collaborative mindset

• BS/MS/PhD in Electrical Engineering or related degree from a reputable institution

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Principal Embedded Design Engineer (Remote)

• Serve as the technical lead for all embedded systems throughout product life cycle

• Able to lead small teams of engineers and technicians

• 10+ years of experience in embedded hardware and firmware design

• Strong proficiency in C/C++ to write application level source code

• Strong knowledge of driver development

• Familiarity with 8051 and ARM architectures

• Strong debugging skills in lab environment including with oscilloscopes, logic analyzers, debuggers, emulators, etc.

• Hands on Experience in preparing Test Plan, Test Estimate

• Experience with Embedded Linux is a strong plus

• B.S. or higher in electrical engineering

 

Lead ASIC Design Engineer/chip Lead - Synthesis/RTL (Santa Clara, CA)

• Define and architect high-performance blocks for the latest, most advanced networking ASICs

• Responsible for micro-architecture, RTL implementation, logic synthesis and timing analysis.

• Work with verification team in validating the design and architecture choices.

• Work with physical design and signal integrity teams to achieve timing closure.

• File patents and participate in patent reviews.

• B.S./M.S. degree in Electrical Engineer, Computer Engineering or Computer Science with at least 14+ years of ASIC experience in design, verification, and architecture.

• Experience in networking ASIC architecture and design, from routing, switching, to security.

• Expertise in packet processing, lookup & scheduler engine, hashing and deep packet-inspection.

• Experience in memory technologies such as DDR3/4, GDDR, and HMC or HBM.

• Experience with EDA tools such as Synopsys Primetime, Cadence Conformal, Atrenta CDC, or formal verification is a plus.

• Experience with security algorithms such as AES-GCM, hash functions such as SHA, MACsec standard (IEEE 802.1AE) and protocols such as IPsec.

• -Familiar with 10G/25G/100G/400G Ethernet, Interlaken, 802.11, OTN and other standards.

• Above experience is not a must for candidature but good to have 

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Sr. Java Developer  (Remote - In U.S.)

• Design, build and maintain production ready code

• Minimum 5 years of experience writing primarily Java code

• Experience with J2EE., JSP, SQL, SpringMVC, and Rest API

• Experience with AWS or other cloud platforms such as Azure or GCP

• Good knowledge of data structures and algorithms

• Strongly prefer analytical minded engineers

• Bachelor Degree or higher in computer science or similar

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FPGA Designer  (San Diego, CA)

• Experience in design , development and verification of complex FPGAs.

• RTL development in Verilog / VHDL.

• Familiarity with Xilinx / Altera FPGAs.

• Familiarity with Xilinx / Altera development / synthesis tools , ModelSim.

• Familiarity with high speed interfaces: PCIe , SPI-4.2 , SFI-4.2 , Gigabit Ethernet , UTOPIA , POS PHY , USB2 / 3 , DDR3 , etc.

• Familiarity with hardware test equipment: High speed DSO , Logic Analyzer , Spectrum Analyzer , Network Analyzers , Traffic Generators , etc.

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Senior Python Software Engineer (Austin, TX, Potentially Remote)

• Responsible for developing, testing, and releasing production code

• Be able to execute full software development life cycle

• 4+ years of experience in writing Python (language) code

• Experience with containers (Docker) and their orchestration

• Experience with Django REST Framework

• Experience with MongoDB, Scrappy, MongoDB, SQL Server, Pandas, and Shell Scripting

• Able to create and customized web applications in Django Python

• Knowledge of Code Commit Bitbucket

• B.S./M.S. in computer science or similar

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Sr. Embedded Hardware/Firmware Engineer (Phoenix, AZ)

• In this position you will spearhead or assist in the design of company's embedded systems including development and debug of all firmware as well as assisting in the development and debug of hardware

• 5+ years of experience in design and development of 8/32-bit architecture systems

• Strong knowledge of C programming with C++ as a plus - Minimum 5 years

• Proficiency in problem solving and troubleshooting technical issues

• Experience with writing application and driver level code

• Experience with embedded RTOS - Embedded Linux is a strong plus

• Experience with debug or both firmware and hardware

• Knowledge of schematic capture and embedded digital/analog circuitry is a strong plus

• Minimum Bachelor's degree in electrical or computer engineering

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Hardware Design  (Cambridge, MA - Possibly Remote)

• Knowledge of Computer architecture

• Knowledge of digital design methodologies and tool flow

• Excellent logic design, debugging

• Application Engineer - Signal Processing and FPGA Design

• Job Summary

• As an Application Engineer for the Signal Processing and FPGA Design application areas, you will partner with our most innovative customers to establish MATLAB and Simulink as a platform for a variety of application areas including:

• Signal Processing and Communication System Design

• Computer Vision and Image Processing System Design

• HDL (VHDL / Verilog) Code Generation and Verification

• Prototyping and Implementing Designs on FPGAs

• A bachelor's degree and 7 years of professional work experience (or a master's degree and 5 years of professional work experience, or a PhD degree) is required.

• Candidates must be willing to travel 25% to 50% of the time

• Additional Qualifications

• Masters degree in Engineering (M.E./M.Tech.)

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Sr. Backend Software Engineer (Remote)

• Contribute to design and development of various infrastructure projects including data collection pipelines, backends to support sensor deployments, production machine learning pipelines and more

• Work with other team members to establish requirements and design various backend systems

• Implement these systems with scalability and reliability in mind

• Design and implement tools for monitoring and alerting

• Experience with AWS or other cloud providers, i.e. Azure, GCP

• Strongly skilled in Python programming

• Knowledge of C++ or willingness to learn it for future use and interaction w/ company’s C++ developers

• B.S. or higher in computer science, engineering, or similar

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DFT Engineer - Verification (Santa Clara, CA)

• B.S./M.S. in Electrical / Electronic / Computer Engineering

• Minimum 3-4 years- experience in ASIC Design Verification, with knowledge of Computer Architecture.

• Experience in any computer architecture such as x86 or ARM domain based SOCs/Cores is a plus.

• Must have excellent knowledge of design & verification flows.

• Excellent hands-on debug skills.

• Any Verification methodology involving OOPs concepts C++, OVM/UVM Methodology knowledge and experience is a plus.

• Strong Verilog, System Verilog, PLI/DPI interface, SystemC or C/C++, Perl/shell script programming skills.

• Must have good communication skills and the ability and desire to foster a team environment

• Good prior experience with DFT verification for DFT DV position.

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Senior Engineer / Technical Lead/ Project Lead  (Austin, TX)

• Requirements capture, verification, and system integration

• Testbench development for the verification of RTL blocks using SystemVerilog OVM/UVM

• Understanding of DO-254

• This position requires these skills and abilities:

• *RTL coding and simulation Testbench development for the verification of RTL blocks using SystemVerilog

• Familiarity with data interfaces (PCIe, DDR, Ethernet, sRIO, ARINC-429, etc.)

• Familiarity with revision control concepts and tools (e.g. Clearcase, Subversion)

• Ability to work with minimal supervision, part of a team of engineers with a variety of skills and backgrounds, matrixed into projects with aggressive schedules and frequent milestones

• Strong oral and written communication skills and the ability to document and present one's work and status

• Bachelor's Degree in applicable engineering field

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Environmental Engineer (Milwaukee, WI)

Qualifications:

• Degree in Geology or Environmental Engineering

• Experience working in consultancy

• Production of Remediation Method Statements, supervision of remediation works and production of Validation Reports

• Experience in soil, and groundwater risk assessments

• Research and keep up to date with current contamination topics & legislation Liaison with Clients and Regulators including Local Authorities and the Environment Agency

• Experience in risk management, regulations and associated testing 

• Knowledge of logging soils and rocks etc.

• Excellent communication and report writing skills

• Site monitoring including soil and groundwater

• Planning, execution and reporting of Phase 1 and Phase 2 site investigations

• Logging soil and rock samples

• Coordinating lab testing

• Conducting soil and groundwater risk assessments

• Client/regulation communications

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Sr. Sales Engineer/Account Manager (Santa Barbara, CA)

• Min 5 yrs working in sales, preferably in the electronics industry 

• Experience in working with sales and engineering staff to deliver high-quality presentations and information to clients.

• Demonstrated success in growing sales revenues.

• Ability to comprehend and explain complex engineering concepts in simple, effective terms.

• Successful experience in driving innovation as a way to increase sales.

• Successful experience in developing and delivering persuasive presentations to audiences ranging from small groups of clients to large trade show audiences.

• Excellent oral and written communication skills.

• Excellent time management skills.

• Bachelor’s or Master’s degree (business, marketing, or engineering a plus)​

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Physical Designers (Sunnyvale, CA)

• DFT Skills : Fundamentals of SCAN stuck-at and at-speed techniques. Expertise in handling Mentor Graphics EDT logic. Knowledge on chip clock controller (OCC). Pattern generation with Mentor Graphics TestKompress Tool.

• Good knowledge in BSCAN operations.

• Good Knowledge in MBIST Operations, Expertise in handling Synopsyss SMS tool sets (Integrator, Builder, Yield Accelerator)

• Excellent track of pattern simulation and coverage analysis.

• Expert in writing testbenches (Verilog, system Verilog) and tests for different components like PLL, ADC etc for generating ATE vectors.

• Skills: ASIC and SoC design experience with specialization in DFT. Communication and team skills. Additional Experience needed BS +experience, MS + experience.

 

ASIC Design Engineer (Milpitas, CA)

• Strong Skills and Aptitude for Design

• Proven Experience in ASIC & FPGA Design Flows

• Familiarity with Processor based Designs, Verilog/System Verilog/VHDL Coding Skills

• Familiarity with Standards related to USB, Ethernet, Network Protocols

• Familiarity and Hands-on Experience in ASIC & FPGA Areas(Tools) - Synthesis (DC), Linting, Timing Closure (PT), DFT (Mentor), FPGA (Synplicity)

 

Design Engineer (New York, NY)

• Strong knowledge in IC chip design methodology.

• Sound knowledge of RTL design and front-end design tools and flows.

• Good experience in Synthesis, Constraint Development, Linting and CDC

• Good communication skills to work in a cross functional international team with analog, digital and software design engineers

• The design engineer should architect digital subsystem together with system designer.

• Specification update and documentation of the design.

• IP development and coding using the coding style followed by RFA.

• Construction of module test cases and perform basic verification of the IP developed.

• Perform synthesis, constraints development, LINT and CDC check

 

Staff Design Engineer – ASIC/RTL/SATA (San Diego, CA)

• The candidate will be working for ASIC RTL design team which develops processing system SoC. As subsystem design lead he/she will lead design activities for High Speed IO sub-system. The subsystem will have SATA, USB3.0, Display Port/HDMI IPs and high-speed Serdes and multiple AXI interconnect bridges and DMAs.

• The SoC integration will involve micro-arch definition, RTL design, timing constraints and design quality checks like lint/cdc. As part of design team, the candidate will own design feature/IP and will support for verification/validation of the IP/System. The ideal candidate will have excellent micro-architecture/design/timing knowledge and IP/SoC development expertise for at least one or 2 SoCs involving SATA/USB3.0. It is highly desirable that candidate has excellent verbal and written communication skills. He should be able to mentor young team member in addition to contribution as Individual contributor.

• Key skills Bachelors/Masters with 10+ yrs of relevant experience in RTL design/SoC Integration

• Hands on expertise in SATA, USB3.0 protocols and design experience

• Knowledge in SATA, USB Serdes-phy integration is required

• Work experience in ARM and AXI bus based system, knowledge of memory controller required

• Must be able to create synthesis constraints based on design requirements

• Must have knowledge in clock-domain crossing(CDC, Spyglass, 0in),Linting (Spyglass) and other RTL quality checks

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RTL Design Engineer - ASIC Domain  (Mountain View, CA)

• Experience in the digital design.

• Micro-architecture and RTL coding expertise, experience working on Multi clock domain designs(CDC).

• Familiar with Bus protocols AMBA AXI/AHB, APB.

• Familiar with the Low power design concepts.

• Basic knowledge of MBIST and DFT concepts.

• Basic knowledge of front end flows - Lint, CDC.

• Working experience on Revision control flows and Tool checks

• Clearcase/Spyglass/Verdi

• Lint & CDC checks

• Various simulator

• Timing Constraints definition for Synthesis.

• Synthesis (DC/DCG/DCT) and FV with familiarity of Low power aware Synthesis using UPF.

• Synopsys DC and Conformal LEC tool familiarity.

• Familiar with Power intent formats - UPF/CPF.

• Timing closure basics (STA using Primetime).

• ECO flow.

• Expecting expertise in at least two of the following

• Advance Timing closure - handling multi-mode and multi corner timing closure.

• Formal equivalence checking experience.

• Low power checks - CLP with UPF/CPF.

• Conformal ECO flow.

• Power analysis using PTPX.

 

Physical Design Engineer – ASIC/STAS (San Jose, CA)

• Key areas of responsibility:

• Strong experience in all PD tasks related to ASIC chip design.

• Low Power implementation expertise.

• Expertise in clock tree closure from Frequency/Power/EMC/Reliability perspective.

• Ability to use scripting languages to automate the low.

• Constraints development knowledge and STA experience

• Chip-level Physical verification expertise.

• Must have Power and EMIR analysis expertise.

• Full chip level Pad Ring Design Knowledge.

• Exposure to Cadence tools.

• Should have good communication skills

 

ASIC Hardware Design Engineer  (Carlsbad, CA)

• RTL design with multiple tape-outs.

• Experience of multi-million gate ASIC design and verification methodologies

• Computer architecture Knowledge

• Experience in logic design with Verilog and/or System Verilog and validation/verification

 

FPGA Designer - Xilinx / Altera (Los Angeles, CA)

• Experience : 8-10 Years

• Job Specifications :

• Complex FPGA projects with a plurality of FPGA designers.

• Place & route flows, pinning, timing optimization for Xilinx and / or Altera

• Tool: Modelsim, Xilinx Vivado, Altera Quartus.

• Work environment: VHDL, Linux, make, revision management, preferably with Git.

• FPGA interface: High-speed transceivers (up to 25 Gbps), DDR4 memories.

• Xilinx Scale Ultra or Ultra Scale +

 

FPGA Lead Engineer – RTL/Porting (San Jose, CA)

• Preferred Qualification: B.Tech / M.Tech

• Experience: 8 - 12 yrs

• Salary: As per the industry standards

• Skills:

• RTL + Porting

• Experience with Xilinx & Altera

• Proficient in Verilog & VHDL

• Desired Candidate Profile :

• A minimum of 8 years professional engineering experience.

• Tasks will include development of Firmware Requirements Specifications for FPGA designs, VHDL - based RTL and functional design, timing analysis, simulation, and integration of FPGA designs into hardware.

• Extensive experience in developing optimal FPGA architectures based on high-level requirements.

• RTL coding of the design in VHDL or Verilog.

• Proficiency with VHDL for configuring FPGAs.

• Proficiency with functional verification test flow using VHDL with assertions.

• Should have Good Communication skills.

• Must be very good in Verilog programming/ Debugging.

 

FPGA Lead  (Sunnyvale, CA)

• A minimum of 8 years professional engineering experience.

• Tasks will include development of Firmware Requirements Specifications for FPGA designs,

• VHDL based RTL and functional design, timing analysis, simulation, and integration of FPGA designs into hardware.

• Extensive experience in developing optimal FPGA architectures based on high-level requirements.

• RTL coding of the design in VHDL or Verilog.

• Proficiency with VHDL for configuring FPGAs.

• Proficiency with functional verification test flow using VHDL with assertions.

• Should have Good Communication skills.

• Must be very good in Verilog programming/ Debugging/ able to write synthesizable codes.

 

FPGA Design Engineers  (San Diego, CA)

• BE/B.Tech in electronics

• Experience in working with FPGAs (Altera or Xilinx)

• Architecture design for FPGA logics

• RTL Coding in VHDL or Verilog

• FPGA simulation using Modelsim or other simulation tools

• Testing FPGA on board

• Debugging FPGA issues

 

FPGA LTE Engineer  (San Jose, CA)

• A Senior FPGA Engineer/Tech lead will be part of a world-class, highly motivated, highly skilled team of wireless (LTE) system engineers who are committed to deliver carrier grade wireless equipment to customers in various verticals starting from WISP to Federal Governments. Candidate should be a firm believer of Cambiums mission, Connecting the Un-Connected and Under-Connected.

• The candidate should have overall experience of 7-12 years with most of this experience in Wireless (LTE/3G/2G) RF Digital Front end development and will be an individual contributor. He/She should have the ability to

• Develop, enhance, integrate with system the digital RF front end blocks (DDC/DUC/CFR/DPD) into LTE based system

• Performance verification and validation of developed modules in FPGA based prototypes and integrate with baseband and RF subsystems.

• Specific Knowledge/Skills

• Strong experience with LTE/3G/2G digital front end design in Verilog/VHDL and integration in FPGA in at least one of FPGA platforms Xilinx or Altera.

• Experience with CPRI interface.

• Strong in FPGA development including

• RTL design and functional simulation using Verilog and VHDL

• SDC timing constraints

• Design methods to obtain timing closure and fit, flor planning place and route optimization in FPGA.

• Xilinx ISE tool or Altera Quartus experience

• Experience with logic synthesis and floor planning tools (Synopsis, Cadence)

• Experience with C programming is highly desirable

 

FPGA/RTL Architect – VHDL/Xilinx/Altera   (Irvine, CA)

• 10 -15 years- experience in FPGA/ RTL Architecture.

• Expertise in designing and implementing FPGA designs in VHDL for Xilinx, Altera and Lattice FPGA devices

• Good experience in various high speed environments, design concepts, multi-clock domains and integrating IP cores in the FPGA design

• Hands on experience in static timing analysis from FPGA and system level.

• Hands on experience in soft processors like NIOS, MicroBlaze based designs

• Designing and writing well-documented, high quality and synthesis-friendly RTL.

• Experience in Logic design / micro-architecture / RTL coding is a must.

• Strong understanding of FPGA architecture and tool flow

• Strong experience with debugging of failures on hardware board

• Experience in defining and performing FPGA module level integration and test plans

• Experience in resolving FPGA module level integration and test issues in hands-on lab environments

• Good understanding of power sensitive designs and power consumption methodology

 

FPGA Developer (Denver, CO)

• Responsibilities:

• Architect and implement new FPGA applications (synthesis, place & route, static timing analysis, documentation)

• Architecting and coding FPGA designs in a hardware description language

• Producing design documents

• Performing timing analysis and floor planning

• Research and evaluate a variety of cutting-edge FPGA hardware and technologies

• Maintain & enhance the existing hardware code base

• Liaise directly with software and other design teams

• Conduct lab debugging and characterization of new hardware

• Candidate Requirements:

• Solid Hardware Engineering experience, especially with FPGA

• Strong skills in RTL logic design (Verilog) and verification

• Knowledge of the TCP/IP stack

• Strong working knowledge of either XILINX or ALTERA FPGA design flow

 

FPGA Design Engineer  (Dallas, TX)

• Looking for expert FPGA Design engineer with RTL Design [VHDL/Verilog] and Design Simulation experience [industry standard tools from Cadence, Synopsys] along with Board level testing of the FPGA designs. Hands-on FPGA Design experience along with exposure to System level testing of the FPGA design will be an ideal fit for this position.

• Proven track record of designing, developing, prototyping, and testing high speed FPGA designs

• Experience in Verilog programming & experience with Xilinx devices and development tools

• Design and Debug @ Platform level including HW RTL and Board level testing.

• System Integration Testing of FPGA Design with Software drivers will be real value addition

• Understanding of SW Drivers and Exposure to Integration testing before SW release

 

VLSI Design Engineer - FPGA (San Jose, CA)

• Selected candidate will be working for high speed FPGA Designing and project location will be Europe

• Job Requirement:

• Complex FPGA projects with a plurality of FPGA designers.

• Place & route flows, pinning, timing optimization for Xilinx and / or Altera

• Tool: Modelsim, Xilinx Vivado, Altera Quartus.

• Work environment: VHDL, Linux, make, revision management, preferably with Git.

• FPGA interface: High-speed transceivers (up to 25 Gbps), DDR4 memories.

• Xilinx Scale Ultra or Ultra Scale +

• Must have skills:

• 5+ Years of experience in FPGA Design and development

• RTL Coding through VHDL more preferable

• Should have worked for as much as highest speed FPGA's (Prefered speed is more than 1Gbps)

 

Principal Design Engineer  (Los Angeles, CA)

• BE/BTech/BS in Electrical or Computer Engineering, Masters degree is a plus

• 10+ years of relevant experience

• Must have a strong background in technical disciplines relating to ASIC design with equal emphasis on the following:

• Architecture and Microarchitecture development

• System Verilog RTL Design coding

• Block and Chip-Level Verification with UVM

• Pre-Silicon Design Emulation strategies utilizing Xilinx FPGA

• Synthesis with Design Compiler & PrimeTime Static Timing Analysis Closure

• Mentor DFT Power-Aware Compression Flow and Vector Stuck-At / Transition / Bridging Vector Generation

• Functional ATE Vector Generation

 

FPGA Prototyping Flow Engineer  (Portland, OR)

• Expertise in the languages: Perl, Tcl and Verilog

• Expertise in the use of make

• Experience in engineering flow development

• Exposure to FPGA compile tools, Xilinx tools a must

• Good SW debug and problem solving skills

 

 

Senior OpenCL (FPGA) Engineer (Santa Clara, CA)

• Looking for experienced OpenCL (FPGA) programmers who have worked on Altera or Xilinx SDKs using OpenCL or DSPBuilder programming. The candidate must have solid knowledge of the programming model to extract the best performance out of the FPGAs. He must also have demonstrable expertise in tuning algorithms for applications. A good understanding of FPGAs is also required. In this job, the candidate will be working with a team in US and India to implement exciting new technologies in the field of machine learning, SQL search, video transcoding, networking and other applications where FPGA acceleration is important. Additional knowledge in applications is a big plus. Knowledge of BSP (board support packages), Verilog HDL, hardware DMA engines etc. is another big plus.

• In this role, you will:

• Rewrite or develop algorithms for FPGA acceleration using OpenCL (and/ or DSPBuilder) and (optionally) BSPs.

• Knowledge of compilation tools and OpenCL tools by Altera or Xilinx.

• Debug for functionality and performance for OpenCL acceleration.

• Work with teams local and remote to develop products.

• Required credentials and skills:

• Min: Bachelor s in Computer Science, Math, Electrical/ Electronics or related fields

• Five years experience in programming with off-load acceleration (OpenCL, CUDA, etc.)

• Bachelors/Masters Degree in Electrical Engineering

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Project Lead  (Irvine, CA)

• Hands-on experience on FPGA programming from requirements till validation

• Strong expertise in RTL programming, verification and validation.

• Proven experience in delivering at least one complex FPGA design project

• Proven experience in a project with FPGA with DDR2/3 controller IP, Softcore processor (such as Altera NIOS-II or Xilinx MiroBlaze or ARM Core SOC or 8051 core)

• Experience in using third party IP or IP provided by FPGA vendors

• Strong analytical skills and problem solving skills. This is the most critical requirement and ability to understand the problem and solving them in plain English or any programming language is a must

 

​FPGA Engineer (Los Angeles, CA)

• 5-12 years of experience in processor/ASIC emulation

• Solid background and understanding of Digital Design and Processor Architecture

• Simulation acceleration knowledge and must have FPGA experience including partitioning, synthesis, PAR and timing tools, good understanding of Xilinx FPGA architecture

• Strong troubleshooting, analytical and board level debug skills

• Expertise in RTL design, simulation, mapping designs to emulation, improving model performance

• Experience in logic simulators from Synopsys/Mentor/Cadence

• Programming/Scripting Skills C, C++, Perl, Python, Shell, Make file TCI

• Experience in AMBA, AHB, AXI, JTAG and debug protocols

 

FPGA Developer  (Fremont, CA)

• Understanding the requirements document and preparing the design plan

• Preparing the high level design

• RTL development for design

• Integrating third party IP (say for interface logic or DDR2/ 3 controller IP etc)

• Preparing verification plan

• Simulation with Xilinx or ModelSIM

• Synthesizing for area or performance

• Validation on final target board

• RTL debugging and bug- fixing

• Hands- on experience on FPGA programming from requirements till validation

• Strong analytical skills and problem solving skills. This is the most critical requirement and ability to understand the problem and solving them in plain English or any programming language is a must

• Experience in camera or imaging product design

• Expertise in C programming

• DSP or Matlab programming experience

• Algorithm development for camera and image processing

• Experience in USB3.0 or Gigabit Ethernet

• 2 to 4 years. Experience is not a major concern.

 

Lead/Sr. Lead-electronics Design  (Portland, OR)

• Understanding of configuration management, requirements traceability (DOORS) and related processes.

• Experience in DO-160 Qualification Testing

• Knowledge of DO-254, HALT, HASS tests

• . Experience in Product design and development of documents as per DO-254. Plan for Hardware Aspects of Certification (PHAC).

• Strong troubleshooting and testing background. Ability to solve complex electronics HW/FW/SW integration issues.

• Strong technical team leadership and mentoring skills. Ability to coordinate multi-disciplined team.

• Experience in making presentations and communicating with management/customers.

• Project management experience. Strong technical writing and verbal communication skills.

• Desirable: Experience in FPGA development process from Design specification, defining architecture, micro-architecture, RTL design, Timing closure , functional verification, synthesis, and post-Si debug

• Basic Qualifications Search Qualification: BE/B.Tech (ME/M.Tech degree is preferred) in Electronics & communication engineering or equivalent

• Experience: 7 to 10 years of experience in the Hardware Verification, Validation, Design, Development and qualification of aerospace electronics systems.

• Experience in Hardware Verification and Validation

• Experience in Analog and Digital Design and Development

• Strong troubleshooting and testing background. Ability to solve complex electronics HW/FW/SW integration issues.

• Must understand the complete product development lifecycle

 

FPGA Developer  (Philadelphia, PA)

• Hands- on experience on FPGA programming from requirements till validation

• Strong expertise in RTL programming, verification and validation.

• Proven experience in delivering at least one complex FPGA design project

• Proven experience in a project with FPGA with DDR2/ 3 controller IP, Softcore processor (such as Altera NIOS- II or Xilinx MiroBlaze or ARM Core SOC or 8051 core)

• Experience in using third party IP or IP provided by FPGA vendors

• Strong analytical skills and problem solving skills. This is the most critical requirement and ability to understand the problem and solving them in plain English or any programming language is a mus

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Sales Engineer  (San Jose, CA)

• Learn the technical details concerning how our software works and what problems it solves for our clients

• Create new sales and marketing strategies that target B2B customers and positions our products as the best solutions for prospective clients

• Manage customer relations by soliciting and logging client feedback and evaluating the data we receive through digital channels

• Generate high-quality sales leads and follow up after initial meeting

• Identify areas where we can improve customer satisfaction and repeat business, then communicate those issues and possible solutions to upper management

• Set and achieve sales goals and quotas on a monthly and quarterly basis